1. Field of the invention
This invention relates to improvements in semiconductor devices and structures and methods for making them.
2. Description of the prior art
Although many electronic functions can be integrated by high level majority carrier MOS technology, there is a wide class of applications that cannot be realized by MOS technology. Minority carrier technology has a fundamental superiority in blocking high voltages in the off-state and providing high current density and high transconductance in the on-state by means of conductivity modulation of the blocking region. Bipolar devices exhibit high speed and are advantageous in precision electronic applications. Deleterious minority carrier effects, for example, speed limitations due to charge storage and secondary breakdown, as well as the heretofore inability to locally control minority carrier transport, have impeded minority carrier technology.
Virtually all modern silicon semiconductor devices are built on a planar surface commencing with a single crystal substrate or a substrate with slightly doped epitaxial layer. Bipolar base regions (or MOS source and drain regions) are formed by selectively injecting excess dopants to compensate the epitaxial film in order to yield the desired net dopant compensation. The emitter region is formed by a second excess dopant compensation in the base to achieve the desired emitter net dopant compensation. Classical isolation is achieved by selective excess dopant compensation of the collector epitaxial region followed by a long diffusion drive-in. Excess dopant compensation can be realized by ion implantation or chemical deposition followed by a diffusion drive.
Junction isolation limits voltage operation to 100-200 volts. High temperature anneals (&gt;1000.degree. C.) is ordinarily utilized to drive in the dopants or to electrically activate the ion implants. Selectively is typically accomplished by patterning a thermal oxide and utilizing an oxide mask to block the deposition or ion implant from entering the crystalling surface. Hence, diffusions are normally performed in an oxidizing ambient in order to grow a diffusion mask for subsequent depositions. The oxide layer also forms a dielectric layer between the planar silicon surface and the ambient. A thin, thermal silicon dioxide layer electrically improves the abrupt termination of the periodic crystalline lattice by forming an SiO.sub.x region that ties up dangling bonds.
The excess dopant compensation approach alters the naturally occurring scheme of events in that, while accomplishing the desired net doping level, the crystalline lattice periodicity is excessively perturbed by the additional dopant atoms. This is particularly deleterious to minority carrier operation. Interstitial atoms are introduced into the lattice and strain dislocations occur to relieve stress from excess dopant atoms. Although the electrical characteristics are determined in the first order by the net impurities, the crystal characteristics are determined by the total impurity level. The thermal oxidation process introduces further stress and resulting lattice dislocations. In order to enhance diffusion of dopants into silicon, as well as to grow silicon dioxide masking layers, high temperature anneals are employed (typically 1000.degree. C. and higher). The high temperatures, as well as the temperature transitions, introduce further stress damage to the lattice. Additionally, the high temperatures enhance the diffusivity of undesirable impurities into the silicon lattice which further degrade semiconductor performance. Essentially, the excess dopant compensation technique perturbs naturally occurring crystalline perfection, and correspondingly, limits semiconductors performance.
Although the introduction of the planar processing concept over 25 years ago had an amazing impact on the introduction of integrated circuits, it is believed that planar processing will impose limitations on future semiconductor capability. Planar processing generally limits the wafer to one lightly doped epitaxial region which constrains all transistors to be of similar current-voltage capability. Planar processing forces vertical introduction of excess dopants into the planar surface by ion implantation or diffusion with an oxide mask. The vertical dopant introduction limits the vertical penetration range of net excess dopant compensation and restricts transistor operation to near the planar surface. Attempts to increase vertical dopant penetration result in increased lattice damage which degrades semiconductor performance. Planar processing results in planar surface termination of depletion layers which builds in a surface sensitivity and yield degradation. Planar devices are particularly sensitive to the masking operation which can cause surface defects. Planar devices are also sensitive to oxide quality and surface charge reflection through the oxide. Consequently, planar device reliability tends to be very dependent on ion control, particularly sodium and halides. Moreover, non-silicon based compound semiconductors have severe materials, electrical, and cost limitations in many applications.